Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 9043b2d5c3be4ca99f9da59e1ea265b5.D9334DB0318140F79E8F248D0F9858F9.1 Target Package: tqg144
Registration ID __0_0_0 Target Speed: -3
Date Generated 2019-11-26T21:51:30 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3067 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3067 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=11
  • AGG_IO=11
  • AGG_LOCED_IO=11
  • AGG_SLICE=4
  • NUM_BONDED_IOB=11
  • NUM_BSLUTONLY=7
  • NUM_BSUSED=7
  • NUM_LOCED_IOB=11
  • NUM_LOGIC_O6ONLY=7
  • NUM_SLICEX=4
  • NUM_SLICE_CYINIT=7
  • NUM_SLICE_UNUSEDCTRL=4
NetStatistics
  • NumNets_Active=22
  • NumNodesOfType_Active_BOUNCEIN=1
  • NumNodesOfType_Active_DOUBLE=21
  • NumNodesOfType_Active_GENERIC=15
  • NumNodesOfType_Active_IOBIN2OUT=11
  • NumNodesOfType_Active_IOBOUTPUT=11
  • NumNodesOfType_Active_LUTINPUT=28
  • NumNodesOfType_Active_OUTBOUND=15
  • NumNodesOfType_Active_OUTPUT=7
  • NumNodesOfType_Active_PADINPUT=7
  • NumNodesOfType_Active_PADOUTPUT=4
  • NumNodesOfType_Active_PINBOUNCE=2
  • NumNodesOfType_Active_PINFEED=35
  • NumNodesOfType_Active_QUAD=63
  • NumNodesOfType_Active_SINGLE=14
SiteStatistics
  • IOB-IOBM=6
  • IOB-IOBS=5
  • SLICEX-SLICEL=3
SiteSummary
  • IOB=11
  • IOB_IMUX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=7
  • LUT6=7
  • PAD=11
  • SLICEX=4
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:7]
  • SLEW=[SLOW:7]
  • SUSPEND=[3STATE:7]
 
Pin Data
IOB
  • I=4
  • O=7
  • PAD=11
IOB_IMUX
  • I=4
  • OUT=4
IOB_INBUF
  • OUT=4
  • PAD=4
IOB_OUTBUF
  • IN=7
  • OUT=7
LUT6
  • A3=7
  • A4=7
  • A5=7
  • A6=7
  • O6=7
PAD
  • PAD=11
SLICEX
  • A=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • B=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • C=1
  • C3=1
  • C4=1
  • C5=1
  • C6=1
  • D=3
  • D3=3
  • D4=3
  • D5=3
  • D6=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 172 150 0 0 0 0 0
bitgen 154 154 0 0 0 0 0
map 166 162 0 0 0 0 0
netgen 6 6 0 0 0 0 0
ngc2edif 20 20 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 170 170 0 0 0 0 0
par 162 162 0 0 0 0 0
trce 162 162 0 0 0 0 0
xst 192 192 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2019-08-12T18:20:33
PROP_intWbtProjectID=D9334DB0318140F79E8F248D0F9858F9 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx9 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=tqg144 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_SCHEMATIC=8 FILE_UCF=1
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_AND2=1 XST_NUM_AND3=1 XST_NUM_AND4=1 XST_NUM_INV=1
XST_NUM_OR3=1 XST_NUM_OR4=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=1 NGDBUILD_NUM_AND3=13 NGDBUILD_NUM_AND4=11 NGDBUILD_NUM_IBUF=4
NGDBUILD_NUM_INV=28 NGDBUILD_NUM_OBUF=7 NGDBUILD_NUM_OR3=3 NGDBUILD_NUM_OR4=4
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=1 NGDBUILD_NUM_AND3=13 NGDBUILD_NUM_AND4=11 NGDBUILD_NUM_IBUF=4
NGDBUILD_NUM_INV=28 NGDBUILD_NUM_OBUF=7 NGDBUILD_NUM_OR3=3 NGDBUILD_NUM_OR4=4
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-3-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5