Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 9043b2d5c3be4ca99f9da59e1ea265b5.E4AA2151122540FF88DC1C63D98F74EA.1 Target Package: tqg144
Registration ID __0_0_0 Target Speed: -3
Date Generated 2019-12-02T14:58:32 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3067 MHz
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz CPU Speed 3067 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=6
  • AGG_IO=6
  • AGG_SLICE=83
  • NUM_BONDED_IOB=6
  • NUM_BSLUTONLY=183
  • NUM_BSUSED=183
  • NUM_LOGIC_O6ONLY=183
  • NUM_SLICEX=83
  • NUM_SLICE_CYINIT=183
  • NUM_SLICE_UNUSEDCTRL=83
NetStatistics
  • NumNets_Active=192
  • NumNodesOfType_Active_BOUNCEIN=11
  • NumNodesOfType_Active_DOUBLE=113
  • NumNodesOfType_Active_GENERIC=9
  • NumNodesOfType_Active_IOBIN2OUT=6
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_LUTINPUT=632
  • NumNodesOfType_Active_OUTBOUND=214
  • NumNodesOfType_Active_OUTPUT=208
  • NumNodesOfType_Active_PADINPUT=3
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=14
  • NumNodesOfType_Active_PINFEED=635
  • NumNodesOfType_Active_QUAD=25
  • NumNodesOfType_Active_SINGLE=213
SiteStatistics
  • IOB-IOBM=3
  • IOB-IOBS=3
  • SLICEX-SLICEL=23
  • SLICEX-SLICEM=20
SiteSummary
  • IOB=6
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=3
  • LUT6=183
  • PAD=6
  • SLICEX=83
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:3]
  • SLEW=[SLOW:3]
  • SUSPEND=[3STATE:3]
 
Pin Data
IOB
  • I=3
  • O=3
  • PAD=6
IOB_IMUX
  • I=3
  • OUT=3
IOB_INBUF
  • OUT=3
  • PAD=3
IOB_OUTBUF
  • IN=3
  • OUT=3
LUT6
  • A1=5
  • A2=5
  • A3=97
  • A4=159
  • A5=183
  • A6=183
  • O6=183
PAD
  • PAD=6
SLICEX
  • A=65
  • A1=3
  • A2=3
  • A3=33
  • A4=62
  • A5=65
  • A6=65
  • B=43
  • B1=1
  • B2=1
  • B3=21
  • B4=31
  • B5=43
  • B6=43
  • C=38
  • C1=1
  • C2=1
  • C3=29
  • C4=36
  • C5=38
  • C6=38
  • D=37
  • D3=14
  • D4=30
  • D5=37
  • D6=37
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 173 151 0 0 0 0 0
bitgen 155 155 0 0 0 0 0
map 167 163 0 0 0 0 0
netgen 6 6 0 0 0 0 0
ngc2edif 20 20 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 171 171 0 0 0 0 0
par 163 163 0 0 0 0 0
trce 163 163 0 0 0 0 0
xst 193 193 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2019-09-09T20:36:55
PROP_intWbtProjectID=E4AA2151122540FF88DC1C63D98F74EA PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=false
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_SCHEMATIC=6
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_AND2=1 XST_NUM_INV=1 XST_NUM_NAND2=1 XST_NUM_NAND3=1
XST_NUM_OR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=32 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=187 NGDBUILD_NUM_NAND2=218
NGDBUILD_NUM_NAND3=94 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_OR2=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=32 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_INV=187 NGDBUILD_NUM_NAND2=218
NGDBUILD_NUM_NAND3=94 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_OR2=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-3-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5