Mod10Cnt Project Status (12/04/2019 - 11:04:58)
Project File: Mod10Cnt.xise Parser Errors: No Errors
Module Name: Mod10Cnt Implementation State: Synthesized
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 20 5720 0%
Number of fully used LUT-FF pairs 0 20 0%
Number of bonded IOBs 7 102 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentΌφ 12 4 11:04:57 201901 Warning (1 new)0
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/04/2019 - 11:04:58