T_D_JKFF_E_SET Project Status (12/03/2019 - 19:50:25) | |||
Project File: | T_D_JKFF_E_SET.xise | Parser Errors: | No Errors |
Module Name: | T_D_JKFF_E_SET | Implementation State: | Synthesized |
Target Device: | xc6slx9-3tqg144 |
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No Errors |
Product Version: | ISE 14.7 |
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1 Warning (1 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice LUTs | 4 | 5720 | 0% | |
Number of fully used LUT-FF pairs | 0 | 4 | 0% | |
Number of bonded IOBs | 4 | 102 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ȭ 12 3 19:50:23 2019 | 0 | 1 Warning (1 new) | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |