T_D_JKFF_E_SET Project Status (12/03/2019 - 19:50:25)
Project File: T_D_JKFF_E_SET.xise Parser Errors: No Errors
Module Name: T_D_JKFF_E_SET Implementation State: Synthesized
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 4 5720 0%
Number of fully used LUT-FF pairs 0 4 0%
Number of bonded IOBs 4 102 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentȭ 12 3 19:50:23 201901 Warning (1 new)0
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/03/2019 - 19:50:25